The present invention relates generally to reticle and integrated circuit design and fabrication systems. More specifically, the invention relates to mechanisms for inspecting reticles and integrated circuits.
Generation of reticles and subsequent optical inspection of such reticles have become standard steps in the production of semiconductors. Initially, circuit designers provide circuit pattern data, which describes a particular integrated circuit (IC) design, to a reticle production system, or reticle writer. The circuit pattern data is typically in the form of a representational layout of the physical layers of the fabricated IC device. The representational layout typically includes a representational layer for each physical layer of the IC device (e.g., gate oxide, polysilicon, metallization, etc.). Each representational layer is typically composed of a plurality of polygons that define a layer's patterning of the particular IC device.
The reticle writer uses the circuit pattern data to write (e.g., typically, an electron beam writer or laser scanner is used to expose a reticle pattern) multiple reticles that will later be used to fabricate the particular IC design. A reticle or photomask is an optical element containing transparent and opaque, semi-transparent, and phase shifting regions which together define, the pattern of coplanar features in an electronic device such as an integrated circuit. In general terms, reticles are used during photolithography to define specified regions of a semiconductor wafer for etching, ion implantation, or other fabrication processes. For many modern integrated circuit designs, an optical reticle's features are between about 1 and about 5 times larger than the corresponding features on the wafer. For other exposure systems (e.g., x-ray, e-beam, and extreme ultraviolet) a similar range of reduction ratios also apply.
Optical reticles are typically made from a transparent medium such as a borosilicate glass or quartz plate on which is deposited on an opaque and/or semi-opaque layer of chromium or other suitable material. However, other mask technologies are employed for direct e-beam exposure (e.g., stencil masks), x-ray exposure (e.g., absorber masks), etc. The reticle pattern may be created by a laser or an e-beam direct write technique, for example, both of which are widely used in the art.
After fabrication of each reticle or group of reticles, each reticle is typically inspected by illuminating it with light emanating from a controlled illuminator. An optical image of the reticle is constructed based on the portion of the light reflected, transmitted, or otherwise directed to a light sensor. Such inspection techniques and apparatus are well known in the art and are embodied in various commercial products such as many of those available from KLA-Tencor Corporation of San Jose, Calif.
During a conventional inspection process, a target image of a test structure on the reticle is typically compared to a reference image. The reference image is either generated from the circuit pattern data or from an adjacent die on the reticle itself. Either way, the target image features are analyzed and compared with corresponding features of the reference image. Each feature difference is then compared against a threshold value. If the target image feature varies from the reference feature by more than the predetermined threshold, a defect is defined. Similar techniques may be utilized to inspect an integrated circuit (IC).
Unfortunately, these inspection mechanisms frequently result in false defects when the target images significantly differ from their corresponding reference images and these differences are not caused by “real” defects. Several different effects may contribute to the target images differing from the reference images. When the target structures are fabricated from a set of original design patterns which are also used as the reference images, the fabrication process itself introduces discrepancies between the target structures and the reference images. By way of examples, the target structures may become tapered and reduced in size. Target structure corners may also become rounded and/or warped, while edges may become roughened. Imaging of the target structures during inspection also introduces discrepancies between the reference and target images. The imaging process may result in edge enhancement or suppression and contrast changes between the substrate and material, as compared with the design patterns (or reference images). Edges may also appear thickened.
One technique for reducing the number of false defects includes altering the reference image to simulate imaging and/or processing effects until the reference image begins to look like the target image. Several parameters (e.g., corner rounding) of the reference image are typically changed in an iterative process until the reference image resembles the target image. This iterative process is typically complex and time consuming. Although this iterative process may result in a reference image that resembles the target image, it may also unintentionally add a feature to the reference image that corresponds to a “real” defect in the target image so that capture of “real” defects on the target image is hindered. Since a defect is defined as a difference between the reference image and the target image and the reference image has been altered to resemble the target image, this technique may cause “real” defects on the target to be cancelled by simulated portions of the reference image so that the “real” defect are not found.
Accordingly, there is a need for improved mechanisms for inspecting reticles and integrated circuits so that real defects may be reliable found. Additionally, there is a need for reduction in the discrepancies between the reference and corresponding target images caused by imaging effects resulting from imaging of the corresponding test structures.